I'm Faisal Saeed
Hardware Design Engineer at CoMira Solutions Inc
Design Engineer working on RTL designs and verification. Actively contributes to SoC and UCIe.
A good understanding of Verilog was achieved at Comira during my training, followed by comprehending the concepts of object-oriented programming in SystemVerilog. Subsequently, UVM (Universal Verification Methodology) was learned. Formal verification and UVM-based verification were performed on the integration of FIFO and ALU.
I managed to work as a Lab Assistant at GIKI, Swabi, Pakistan, where I learned more about Siemens S71200 PLC and relay logic.
In addition to my competence in HTML and CSS, I've developed several clones of animated websites, and I'm proficient in Javascript.
